1. Field of the Invention
The present invention relates to a semiconductor device having a local interconnection connecting an interconnection layer to an impurity region adjoining to the same.
2. Description of the Related Art
It has been known that electrically conductive layers can be connected together by a local interconnection without forming an interlayer insulating film and a contact hole. The local interconnection, which does not require the interlayer insulating film and contact hole, can easily achieve high integration of a device. Semiconductor devices having local interconnections are disclosed, for example, in IEEE Transactions on Electron Devices, Vol. ED-34, No. 3, March 1987, PP.682-688 (Reference (1)), and IEEE Jun. 11-12, 1991 VMIC Conference, pp.332-334 (Reference (2)).
The reference (1) discloses a technique in which an impurity region and a gate electrode are connected together using TiN. The reference (2) discloses a technique in which, after forming a gate electrode, a polysilicon layer for forming a local interconnection is formed, and then a surface of the polysilicon layer is turned into silicide to form the local interconnection connecting impurity regions together.
Between the two references (1) and (2) above, contents of the reference (1), in which the local interconnection made of TiN connects the gate electrode and impurity region together, are closer to the present invention, in view of contents of the invention which will be described later. Therefore, the prior art will be described below based on the contents of the reference (1).
FIG. 45 is an equivalent circuit diagram showing a boosting circuit which is an example of the device utilizing the technique disclosed in reference (1). FIG. 46 is a cross section showing a region 100 of FIG. 45.
Referring first to FIG. 45, description will be made in connection with the boosting circuit. In FIG. 45, an MOS transistor 108a and an MOS diode 108b are connected in series between a power terminal receiving a supply voltage Vcc and an output terminal 121. The MOS transistor 108a receives at its gate electrode a control signal .phi..sub.2. A node N between the MOS transistor 108a and MOS diode 108b receives a control signal .phi..sub.5 through a capacitor 120.
An operation of the boosting circuit thus structured will be described below. When the control signal .phi..sub.2 rises from 0 V to Vcc+.alpha., the MOS transistor 108a is turned on, where .alpha. is a voltage not less than a threshold voltage Vth of the MOS transistor 108a. Thereby, the node N is charged to the supply voltage Vcc. Thereafter, the control signal .phi..sub.2 goes to 0 V, and the MOS transistor 108a is turned off.
Then, the control signal .phi..sub.5 rises from 0 V to the supply voltage Vcc, so that the voltage of node N rises to 2 Vcc owing to capacitive coupling. Thereby, a voltage of the output terminal 121 changes to 2 Vcc-Vth. Thereafter, the control signal .phi..sub.5 goes to 0 V. By repeating these operations, the supply voltage Vcc can be raised to the voltage of up to 2 Vcc-Vth regardless of a parasitic capacitance of the node N.
The local interconnection used in the above boosting circuit will be described with reference to FIG. 46.
Referring to FIG. 46, a p-type silicon substrate 101 is provided at its main surface with the MOS transistor 108a and MOS diode 108b. The MOS transistor 108a includes n-type impurity regions 105a and 105b, a gate insulating film 103a, a gate electrode 104a and side wall insulating films 106. Titanium silicide layers (TiSi.sub.2) 107a and 107b are formed on a top surface of the gate electrode 104a and surfaces of the n-type impurity regions 105a and 105b.
The MOS diode 108b includes n-type impurity regions 105b and 105c, a gate insulating film 103b, a gate electrode 104b, side wall insulating films 106 and a TiN layer 110 forming a local interconnection. The titanium silicide layers 107a and 107b are formed on a surface of the n-type impurity region 105c and a top surface of the gate electrode 104b, respectively.
The TiN layer 110 is formed over a region extending from the top surface of the gate electrode 104b via the surface of the side wall insulating film 106a to the surface of the n-type impurity region 105b. Thereby, the gate electrode 104b and n-type impurity region 105b are electrically connected together. The p-type silicon substrate 101 is provided at its main surface with element isolating and insulating films 102 between which the MOS transistor 108a and MOS diode 108b are located.
The TiN layer 110 directly connects the gate electrode 104b and the n-type impurity region 105b together, without using a contact hole. Therefore, high integration of a pattern layout can be achieved.
Referring to FIGS. 47 to 51, a method of manufacturing the semiconductor device having the above structures will be described below. FIGS. 47 to 51 are cross sections showing 1st to 5th steps in the process of manufacturing the semiconductor device.
Referring first to FIG. 47, the element isolating and insulating films 102 are formed on the main surface of the p-type silicon substrate 101. Then, a thermal oxidation method or the like is used to form an insulating film, on which a polysilicon layer is formed by, for example, the CVD (Chemical Vapor Deposition) method. These insulating layer and polysilicon layer are patterned to form the gate insulating films 103a and 103b as well as the gate electrodes 104a and 104b.
Using the gate electrodes 104a and 104b as well as the element isolating and insulating films 102 as a mask, n-type impurity is implanted into the main surface of the silicon substrate 1 to form the n-type impurity regions 105a, 105b and 105c. Then, an insulating film covering the gate electrodes 104a and 104b are formed on the whole main surface of the silicon substrate 101 by, for example, the CVD method. Anisotropic etching is effected on the insulating film to form the side wall insulating films 106 on side walls of the gate electrodes 104a and 104b.
Referring to FIG. 48, sputtering or the like is carried out to deposit a Ti layer 109 on the whole main surface of the silicon substrate 101. Referring to FIG. 49, an RTA (Rapid Thermal Annealing) processing is effected on the Ti layer 109 at a temperature in the range of 600.degree. C. to 700.degree. C. for 30 seconds. Thereby, at least a surface region of the Ti layer 109 is nitrided to form the TiN layer 110.
Meanwhile, titanium silicide layers 107a and 107b are formed at interfaces between the Ti layer 109 and the n-type impurity regions 105a, 105b and 105c and between the Ti layer 109 and the gate electrodes 104a and 104b, respectively. This technique is generally referred to as Salicide (Self-aligned Salicide). In the Silicide processing, the side wall insulating films 106 serve to isolate the gate electrodes 104a and 104b and the n-type impurity regions 105a, 105b and 105c from each other for preventing short-circuit therebetween.
Referring to FIG. 50, lithography is carried out to form a resist pattern 111 covering a portion at which the local interconnection is to be formed. Referring to FIG. 51, dry etching is effected on the TiN later 110 to pattern the same using the resist pattern 111 as a mask. Then, the resist pattern 111 is removed. Thereby, the local interconnection made of the TiN layer and electrically connecting the gate electrode 104b and the n-type impurity region 105b together is completed.
Instead of the above method, the TiN layer 110 forming the local interconnection may be formed by a following method. After forming the Salicide structure, the surface layer thereof, i.e., TiN layer 110 is removed, and a new TiN layer, which will form the local interconnection, is deposited by sputtering or the like. This method is more general than the method described before. In view of adhesion of the local interconnection to a base, however, the former method is superior to the latter method, because the TiN layer and the titanium silicide layer are formed of independent layers in the latter method.
The semiconductor device having the conventional local interconnection described above, however, suffers from following two problems. A first problem will now be described below. The TiN layer forming the local interconnection is formed over the region extending from the gate electrode 104b via the side wall insulating film 106 to the impurity region 105c.
Since the titanium silicide layers 107a and 107b and the TiN layer 110 are formed by changing composition of the common Ti layer 109, the adhesion strength thereof is relatively large. However, the adhesion strength between the side wall insulating film 106 and the TiN layer 110 is smaller than the above. Since the side wall insulating film 106 and the TiN layer 110 are in contact with each other through a relatively large contact area, the total adhesion strength between the TiN layer 110 and the base is relatively small. Further, the TiN layer 110 has microscopic patterns. From the foregoing, it can be considered that the possibility of separation of the TiN layer 110 is relatively high.
In accordance with high integration, size of the TiN layer 110 decreases, and hence areas of interfaces between the titanium silicide layers 107a and 107b and the TiN layer 110 decrease. As a result, the adhesion strength between the TiN layer and the base further decreases, so that the possibility of separation of the TiN layer 110 forming the local interconnection further increases.
A second problem will be described below. As already described, dry etching is executed to pattern the TiN layer 110, because the TiN layer 110, i.e., local interconnection having a microscopic pattern is liable to be separated if wet etching is used.
Therefore, the dry etching is inevitably used. However, when dry etching is employed, it is necessary to ensure an appropriate etching selectivity with respect to a base, i.e., a layer under the layer to be patterned. That is, a sufficient etching selectivity must be ensured with respect to two kinds of layers of different compositions, i.e., the titanium silicide layers 107a and 107b and the side wall insulating film 106. This results in a difficulty in selecting the etching conditions.